1. Field of the Invention
The present invention relates to a method of producing semiconductor devices, in particular to a method of forming device isolation structures.
2. Description of the Related Art
Recently, STI (Shallow Trench Isolation) is widely employed for device isolation in a semiconductor device. This is a method of forming a trench in a device isolation region on a semiconductor substrate and burying a device isolation insulator film such as a silicon oxide film in this trench. For burying in the device isolation trench, a film of silicon oxide formed by the high-density plasma CVD (HDP) is commonly employed because it can be buried excellently. When the device isolation trench has a size of 0.1 μm or below as a result of progress in technology of miniaturization, it is difficult to bury the trench sufficiently even with HDP method.
To the contrary, as a trench burying method that does not depend on HDP, there is another method that employs a coat. For example, there is a proposed STI trench burying method that employs a solution of a silazane perhydride polymer (see Japanese Patent 3,178,412 and U.S. Pat. No. 6,191,002). This method includes coating the silazane perhydride polymer solution over a semiconductor substrate that has device isolation trenches formed therein; modifying the coat into a silicon oxide through chemical reaction; performing densification; and removing undesired portions to bury the silicon oxide in the trenches.
Specifically, the chemical reaction in the coat of the silazane perhydride polymer solution is performed by heating in a water vapor ambient, after vaporizing a solvent from the coat. During the heating, the silazane perhydride polymer [(SiH2NH)n] reacts with oxygen resulted from decomposition of the water vapor, gets denatured into the silicon oxide, and produces ammonia. The silicon oxide is then subjected to heating in an inert ambient at 700–100° C. to remove impurities such as ammonia and water for densification.
This method can be applied to burying in a fine device isolation trench with a width of about 0.1 μm. More specifically, (a) the silicon oxide can be buried without generation of voids. In addition, (b) no crack arises because modification from the silazane perhydride polymer into the silicon oxide causes no volume shrink. Alternatively, (c) the silicon oxide to be buried has a high etching resistance that causes no recess during useless etching in the step of wet etching of silicon nitride, for example.
The device isolation trench burying method using the silazane perhydride polymer can be hopefully applied to further fine-patterned LSI (Large Scale Integrated circuits). According to the studies by the Inventors et al., however, there are problems remained to be solved. One of them is a variation caused, corresponding to the width of the trench, in resistance against the wet etching of the silicon oxide buried in the device isolation trench.
Specifically, at a portion where the device isolation trench is narrower in width, an etching rate cannot be reduced sufficiently in the wet etching of the buried silicon oxide. As a result, a surface height of the silicon oxide is lowered compared to a portion where the trench is wider in width. Therefore, the silicon oxide with a uniform thickness cannot be buried in device isolation trenches with various widths.
Another problem is a low wet etching resistance at a portion where the silicon oxide formed by chemical reaction contacts the silicon nitride. The silicon nitride is employed as a mask for forming device isolation trenches and then held until the silicon oxide is buried in the trenches. The coat of the silazane perhydride polymer solution is modified into the silicon oxide through the chemical reaction, then the densified silicon oxide is buried in the trench through CMP (Chemical Mechanical Polishing) process. There are additional steps of removing the silicon nitride using a phosphoric acid and removing the silicon oxide using a buffer hydrofluoric acid. In the step of wet etching using the buffer hydrofluoric acid, the silicon oxide buried in the trench at a portion adjacent to the silicon nitride has a high etching rate, which causes a recess at the boundary around the device isolation region.
FIG. 15 specifically shows a film of silicon oxide 4 buried in device isolation trenches with different widths by the above-described conventional method. The silicon oxide 4 is obtained through densification at 900° C. or below after reaction. In a state shown in FIG. 15, the silicon oxide 4 is densified, then planarized by removing undesired portions using CMP process, and etched using the buffer hydrofluoric acid. As shown, the height of the buried silicon oxide 4 varies depending on the width of the device isolation trench. The device isolation trench with a width as narrow as 0.1 μm causes a recess at a portion of the silicon oxide 4 adjacent to a film of silicon nitride 3 because the portion is etched greatly.
The present invention has an object to provide a method of producing semiconductor devices, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches.